module uart_rx(
    input               sys_clk,
    input               sys_rst_n,
    input               hsv_rst_n,
    input               uart_rxd,

    output reg [8:0]    RED_H_MIN1  , //9'd0   
    output reg [8:0]    RED_H_MAX1  , //9'd48  
    output reg [8:0]    RED_H_MIN2  , //9'd310 //2 byte
    output reg [8:0]    RED_H_MAX2  , //9'd360 //2 byte
    output reg [7:0]    RED_V_MIN   ,
    output reg [7:0]    RED_V_MAX   ,
    output reg [8:0]    YELLOW_H_MIN, //9'd50  
    output reg [8:0]    YELLOW_H_MAX, //9'd75
    output reg [7:0]    YELLOW_V_MIN,
    output reg [7:0]    YELLOW_V_MAX,  
    output reg [8:0]    BLUE_H_MIN  , //9'd200  
    output reg [8:0]    BLUE_H_MAX  , //9'd274 //2 byte
    output reg [7:0]    BLUE_V_MIN  ,
    output reg [7:0]    BLUE_V_MAX  , 
    output reg [7:0]    BLACK_V_MIN , //8'd0   
    output reg [7:0]    BLACK_V_MAX   //8'd70  
    );

    reg          data_valid;
    reg [8:0]    RED_H_MIN1_reg  ;
    reg [8:0]    RED_H_MAX1_reg  ;
    reg [8:0]    RED_H_MIN2_reg  ;
    reg [8:0]    RED_H_MAX2_reg  ;
    reg [7:0]    RED_V_MIN_reg   ;
    reg [7:0]    RED_V_MAX_reg   ;
    reg [8:0]    YELLOW_H_MIN_reg;
    reg [8:0]    YELLOW_H_MAX_reg;
    reg [7:0]    YELLOW_V_MIN_reg;
    reg [7:0]    YELLOW_V_MAX_reg;
    reg [8:0]    BLUE_H_MIN_reg  ;
    reg [8:0]    BLUE_H_MAX_reg  ;
    reg [7:0]    BLUE_V_MIN_reg  ;
    reg [7:0]    BLUE_V_MAX_reg  ;
    reg [7:0]    BLACK_V_MIN_reg ;
    reg [7:0]    BLACK_V_MAX_reg ;

    reg [7:0]   uart_byte_cnt;//字节接受计数器
    reg         uart_done_d0;
    reg         uart_done_d1;

    wire        uart_done;
    wire        uart_done_P;//串口接收单字节完成标志
    wire [7:0]  rx_flag;
    wire [3:0]  rx_cnt;
    wire [7:0]  rxdata;
    wire [7:0]  uart_data;

    assign uart_done_P = (uart_done_d0) && (!uart_done_d1);

    always @(posedge sys_clk) begin
        uart_done_d0 <= uart_done;
        uart_done_d1 <= uart_done_d0;
    end

    always @(posedge sys_clk or negedge sys_rst_n) begin
        if(!sys_rst_n)begin
            uart_byte_cnt <= 1'd0;
            data_valid <= 1'd0;

            RED_H_MIN1_reg   <= 9'd0   ;
            RED_H_MAX1_reg   <= 9'd48  ;
            RED_H_MIN2_reg   <= 9'd310 ;
            RED_H_MAX2_reg   <= 9'd360 ;
            RED_V_MIN_reg    <= 8'd0   ;
            RED_V_MAX_reg    <= 8'd255 ;

            YELLOW_H_MIN_reg <= 9'd50  ;
            YELLOW_H_MAX_reg <= 9'd75  ;
            YELLOW_V_MIN_reg <= 8'd0   ;
            YELLOW_V_MAX_reg <= 8'd255 ;

            BLUE_H_MIN_reg   <= 9'd200 ;
            BLUE_H_MAX_reg   <= 9'd274 ;
            BLUE_V_MIN_reg   <= 8'd0 ;
            BLUE_V_MAX_reg   <= 8'd255 ;

            BLACK_V_MIN_reg  <= 8'd0   ;
            BLACK_V_MAX_reg  <= 8'd70  ;
        end
        else if(uart_done_P)begin
            case (uart_data)
                8'hAF: //接收到起始位
                    begin
                        uart_byte_cnt <= 8'd1;
                    end 
                8'hFA: //接收到结束位
                    begin
                        uart_byte_cnt <= 1'd0;//复位接收计数器
                        data_valid    <= 1'd1;
                    end
                default: 
                    begin
                        case (uart_byte_cnt)
                            8'd1:begin
                                RED_H_MIN1_reg <= uart_data;
                                uart_byte_cnt <= uart_byte_cnt + 1'd1;
                            end 
                            8'd2:begin
                                RED_H_MAX1_reg <= uart_data;
                                uart_byte_cnt <= uart_byte_cnt + 1'd1;
                            end
                            8'd3:begin
                                RED_H_MIN2_reg[8] <= uart_data;
                                uart_byte_cnt <= uart_byte_cnt + 1'd1;
                            end
                            8'd4:begin
                                RED_H_MIN2_reg[7:0] <= uart_data;
                                uart_byte_cnt <= uart_byte_cnt + 1'd1;
                            end
                            8'd5:begin
                                RED_H_MAX2_reg[8] <= uart_data;
                                uart_byte_cnt <= uart_byte_cnt + 1'd1;
                            end
                            8'd6:begin
                                RED_H_MAX2_reg[7:0] <= uart_data;
                                uart_byte_cnt <= uart_byte_cnt + 1'd1;
                            end
                            8'd7:begin
                                RED_V_MIN_reg <= uart_data;
                                uart_byte_cnt <= uart_byte_cnt + 1'd1;
                            end
                            8'd8:begin
                                RED_V_MAX_reg <= uart_data;
                                uart_byte_cnt <= uart_byte_cnt + 1'd1;
                            end
                            8'd9:begin
                                YELLOW_H_MIN_reg <= uart_data;
                                uart_byte_cnt <= uart_byte_cnt + 1'd1;
                            end
                            8'd10:begin
                                YELLOW_H_MAX_reg <= uart_data;
                                uart_byte_cnt <= uart_byte_cnt + 1'd1;
                            end
                            8'd11:begin
                                YELLOW_V_MIN_reg <= uart_data;
                                uart_byte_cnt <= uart_byte_cnt + 1'd1;
                            end
                            8'd12:begin
                                YELLOW_V_MAX_reg <= uart_data;
                                uart_byte_cnt <= uart_byte_cnt + 1'd1;
                            end
                            8'd13:begin
                                BLUE_H_MIN_reg <= uart_data;
                                uart_byte_cnt <= uart_byte_cnt + 1'd1;
                            end
                            8'd14:begin
                                BLUE_H_MAX_reg[8] <= uart_data;
                                uart_byte_cnt <= uart_byte_cnt + 1'd1;
                            end
                            8'd15:begin
                                BLUE_H_MAX_reg[7:0] <= uart_data;
                                uart_byte_cnt <= uart_byte_cnt + 1'd1;
                            end
                            8'd16:begin
                                BLUE_V_MIN_reg <= uart_data;
                                uart_byte_cnt <= uart_byte_cnt + 1'd1;
                            end
                            8'd17:begin
                                BLUE_V_MAX_reg <= uart_data;
                                uart_byte_cnt <= uart_byte_cnt + 1'd1;
                            end
                            8'd18:begin
                                BLACK_V_MIN_reg <= uart_data;
                                uart_byte_cnt <= uart_byte_cnt + 1'd1;
                            end
                            8'd19:begin
                                BLACK_V_MAX_reg <= uart_data;
                                uart_byte_cnt <= uart_byte_cnt + 1'd1;
                            end
                            default: data_valid <= 1'd0;
                        endcase
                    end
            endcase
        end
        else begin
            data_valid <= 1'd0;
        end
    end

    uart_recv u_uart_recv(
        .sys_clk    (sys_clk  ),                  
        .sys_rst_n  (sys_rst_n),                
        .uart_rxd   (uart_rxd ),                 
        .uart_done  (uart_done),                
        .rx_flag    (rx_flag  ),                  
        .rx_cnt     (rx_cnt   ),                  
        .rxdata     (rxdata   ),
        .uart_data  (uart_data)       
    );


always@(posedge sys_clk or negedge hsv_rst_n)
    if(!hsv_rst_n)
        begin
            RED_H_MIN1  <= 9'd0   ;
            RED_H_MAX1  <= 9'd48  ;
            RED_H_MIN2  <= 9'd310 ;
            RED_H_MAX2  <= 9'd360 ;
            RED_V_MIN   <= 8'd0   ;
            RED_V_MAX   <= 8'd255 ;

            YELLOW_H_MIN<= 9'd50  ;
            YELLOW_H_MAX<= 9'd75  ;
            YELLOW_V_MIN<= 8'd0   ;
            YELLOW_V_MAX<= 8'd255 ;

            BLUE_H_MIN  <= 9'd200 ;
            BLUE_H_MAX  <= 9'd274 ;
            BLUE_V_MIN  <= 8'd0   ;
            BLUE_V_MAX  <= 8'd255 ;

            BLACK_V_MIN <= 8'd0   ;
            BLACK_V_MAX <= 8'd70  ;
        end
    else if(data_valid)
        begin
            RED_H_MIN1  <= RED_H_MIN1_reg ;
            RED_H_MAX1  <= RED_H_MAX1_reg ;
            RED_H_MIN2  <= RED_H_MIN2_reg ;
            RED_H_MAX2  <= RED_H_MAX2_reg ;
            RED_V_MIN   <= RED_V_MIN_reg;
            RED_V_MAX   <= RED_V_MAX_reg;
            YELLOW_H_MIN<= YELLOW_H_MIN_reg ;
            YELLOW_H_MAX<= YELLOW_H_MAX_reg ;
            YELLOW_V_MIN <= YELLOW_V_MIN_reg;
            YELLOW_V_MAX <= YELLOW_V_MAX_reg;
            BLUE_H_MIN  <= BLUE_H_MIN_reg ;
            BLUE_H_MAX  <= BLUE_H_MAX_reg ;
            BLUE_V_MIN  <= BLUE_V_MIN_reg;
            BLUE_V_MAX  <= BLUE_V_MAX_reg;            
            BLACK_V_MIN <= BLACK_V_MIN_reg ;
            BLACK_V_MAX <= BLACK_V_MAX_reg ;
        end
    else
        begin
            RED_H_MIN1  <= RED_H_MIN1  ;
            RED_H_MAX1  <= RED_H_MAX1  ;
            RED_H_MIN2  <= RED_H_MIN2  ;
            RED_H_MAX2  <= RED_H_MAX2  ;
            RED_V_MIN   <= RED_V_MIN;
            RED_V_MAX   <= RED_V_MAX;
            YELLOW_H_MIN<= YELLOW_H_MIN;
            YELLOW_H_MAX<= YELLOW_H_MAX;
            YELLOW_V_MIN <= YELLOW_V_MIN;
            YELLOW_V_MAX <= YELLOW_V_MAX;
            BLUE_H_MIN  <= BLUE_H_MIN  ;
            BLUE_H_MAX  <= BLUE_H_MAX  ;
            BLUE_V_MIN  <= BLUE_V_MIN;
            BLUE_V_MAX  <= BLUE_V_MAX; 
            BLACK_V_MIN <= BLACK_V_MIN ;
            BLACK_V_MAX <= BLACK_V_MAX ;
        end
endmodule
